Want Functional Coverage Closure? Don’t kneel to the Almighty Random Constraint Solver 
- Synopsys Users Group (SNUG), 2019 Austin TX, USA. Second Place Presentation Award. paper
Error Injection in a Subsystem Level Constrained Random UVM Testbench
- Design and Verification Conference (DVCon), 2018 San Jose, CA, USA,
Second Place Paper Award. paper slides - Synopsys Users Group (SNUG), 2018 Austin, TX, USA. updated paper slides
Managing Highly Configurable Design and Verification
- Design and Verification Conference (DVCon), 2018 San Jose, CA, USA. paper slides
- Synopsys Users Group (SNUG), 2018 Austin, TX, USA. paper slides
Molding Functional Coverage and Reporting for Highly Configurable IP
- Design and Verification Conference (DVCon), 2016 San Jose, CA, USA. paper poster
- Synopsys Users Group (SNUG), 2016 Austin, TX, USA. paper slides
Performance of a SystemVerilog Sudoku Solver with VCS
- Synopsys Users Group (SNUG), 2015, Austin, TX, USA. paper slides
- IEEE Workshop on Microprocessor and SOC Test and Verification (MTVCon),
2015 Austin, TX, USA. paper slides
Functional Coverage Planning and Automation for Highly Configurable IP
- Design Automation Conference (DAC), 2015 San Francisco, CA, USA.
work-in-progress poster-only
Randomizing UVM Config DB Parameters 
- Design and Verification Conference (DVCon), 2015, San Jose, CA, USA,
Best Poster Award. paper poster
Engineered SystemVerilog Constraints
- Design and Verification Conference (DVCon), 2015, San Jose, CA, USA. fixed paper fixed slides original paper original slides
Global Broadcast with UVM Custom Phasing
VIP Shielding
Making RAL Jump, an Introspective
Interchangeable SystemVerilog Random Constraints
- Synopsys Users Group (SNUG), 2014, Santa Clara, CA, USA. paper slides
- Design Automation Conference (DAC), 2013, Austin, TX, USA.
work-in-progress poster-only
verificationhack 