- CRV – Constrained random verification. Not an often used term, I stumbled across it on a job posting.
- DUT – Design under test. Strictly speaking, test usually refers to post-fabrication testing for manufacture defects, but we use it, too.
- DUV – Design under verification. The HDL design currently undergoing functional verification. This acronym is often used interchangeably with DUT.
- EDIF – Electronic design interchange format. Early vendor-neutral netlist language that closely resembles lisp; essentially superseded by Verilog and VHDL.
- Hack – a horse for ordinary riding; a wooden frame for drying meats, cheeses, etc.; a writer or journalist who produces dull, unoriginal work.
- HDL – Hardware description language. Examples: VHDL, Verilog.
- HVL – Hardware verification language. Examples: C/C++, e, SystemVerilog, Vera, etc.
- OVM – Open verification methodology, refer to OVM World.
- UVM – Unified verification methodology, refer to Accellera.
- Validation – referring to functional verification of an HDL design; i.e. simulation. Gained some traction to differentiate functional simulation from formal verification. Lately, seems to be interchangeable with verification.
- Verification – functional or formal verification of an HDL design, or subset thereof.
- Verification hack – a verification engineer who, in the minds of everyone else out there, has a spectacularly dull life (It’s not like he’s building the Golden Gate Bridge or something exciting.–My Aunt Mildred at Thanksgiving dinner, 2005).
- VMM – Verification methodology manual, refer to VMM Central.
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